1. Technical Field
The present invention generally relates to electronic circuits and in particular to reducing impedance discontinuity in the packaging of electronic circuits.
2. Description of the Related Art
Electronic products, including computers, cellular telephones, and networking systems operate at ever increasing high transmission rates. When operating at high transmission rates, impedance discontinuity decreases the quality of signals in the electronic packages of these devices. Also, excessive capacitance of plated through holes (PTHs) and ball grid arrays (BGAs) can significantly degrade the quality of signals propagating through interconnects of an electronic package.
Numerous techniques have been utilized to improve signal degradation in electronic packaging. For example, an intricate via pattern design, forming an extended, electrically conductive path, has been provided in an effort to decrease impedance discontinuity by increasing the length of the inductive trace. Dramatically increasing the inductive trace increases the length the signal travels; thereby increasing opportunities for signal interference. In addition to increased signal length, the intricate detail of the trace pattern may be impractical to integrate into a currently running process.
In an effort to decrease impedance discontinuities, metal plane layers above the BGA pads on the printed circuit board (PCB) of the electronic packages have been removed. Removing the planar conductive layers above the BGA pads reduces capacitance; however, removing the planes also deteriorates the plane integrity of the printed circuit board of which the electric package is built. In addition to jeopardizing the plane integrity, the routes in which the signals may travel are drastically decreased and the mechanical strength of the PCB is diminished.